收藏本站
MCP2515
1.5
CAN Protocol Engine
1.5.3
ERROR MANAGEMENT LOGIC
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
1.5.1
PROTOCOL FINITE STATE
Transmit Error Counter (TEC), are incremented and
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
1.5.4
BIT TIMING LOGIC
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
1.5.2
CYCLIC REDUNDANCY CHECK
The BTL also provides programmable time segments
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
FIGURE 1-4:
CAN PROTOCOL ENGINE BLOCK DIAGRAM
RX
Bit Timing Logic
Transmit Logic
TX
SAM
Sample<2:0>
Receive
REC
Error Counter
TEC
StuffReg<5:0>
Majority
Decision
BusMon
Comparator
CRC<14:0>
Comparator
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Transmit
Error Counter
Protocol
FSM
ErrPas
BusOff
SOF
Receive<7:0>
RecData<7:0>
Transmit<7:0>
TrmData<7:0>
DS21801G-page 6
Interface to Standard Buffer
Rec/Trm Addr.
? 2003-2012 Microchip Technology Inc.
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
MCP3905EV BOARD DEMO FOR MCP3905
MCP402XEV BOARD EVAL FOR MCP402X
MCP42XXEV BOARD EVALUATION MCP42XX
MCP43XXEV BOARD EVALUATION MCP43XX
MCP46XXDM-PTPLS BOARD PICTAIL DIGI POT MCP4XXX
MCP46XXEV EVAL BOARD FOR MCP46XX
MCP4XXXDM-DB BOARD DAUGHTER DIGIPOT MCP4XXX
MCP6S2XEV BOARD EVALUATION FOR MCP6S2X
相关代理商/技术参数
MCP2515-E 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface
MCP2515-E/ML 制造商:Microchip Technology Inc 功能描述:
MCP2515-E/P 功能描述:网络控制器与处理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
MCP2515-E/SO 功能描述:网络控制器与处理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
MCP2515-E/SORB4 制造商:Microchip Technology Inc 功能描述:
MCP2515-E/ST 功能描述:网络控制器与处理器 IC W/ SPI Inter 125dC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
MCP2515-I 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface
MCP2515-I/ML 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:Stand-Alone CAN Controller with SPI Interface